Vernier Ring Based Pre-bond Through Silicon Vias Test in 3D ICs

Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18 MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code

Spatiotemporal patterns of cortical fiber density in developing infants, and their relationship with cortical thickness: Cortical Fiber Density in Infants

The intrinsic relationship between the convoluted cortical folding and the underlying complex whiter matter fiber connections has received increasing attention in current neuroscience studies. Recently, the axonal pushing hypothesis of cortical folding has been proposed to explain the finding that the axonal fibers (derived from diffusion tensor images) connecting to gyri are significantly denser than those connecting to sulci in both adult human and non-human primate brains. However, it is still unclear about the spatiotemporal patterns of the fiber density on the cortical surface of the developing infant brains from birth to 2 years of age, which is the most dynamic phase of postnatal brain development. In this paper, for the first time, we systemically characterized the spatial distributions and longitudinal developmental trajectories of the cortical fiber density in the first 2 postnatal years, via joint analysis of longitudinal structural and diffusion tensor imaging from 33 healthy infants. We found that the cortical fiber density increases dramatically in the first year and then keeps relatively stable in the second year. Moreover, we revealed that the cortical fiber density on gyral regions was significantly higher at 0, 1, and 2 years of age than that on sulcal regions in the frontal, temporal and parietal lobes. Meanwhile, the cortical fiber density was strongly positively correlated with cortical thickness at several 3-hinge junction regions of gyri. These results significantly advanced our understanding of the intrinsic relationship between the cortical folding, cortical thickness and axonal wiring during early postnatal stages

Spatial Distribution of Water Risk Based on Atlas Compilation in the Shaanxi Section of the Qinling Mountains, China

Global climate change and rapid socio-economic development have increased the uncertainty in water resource systems and the complexity of water risk issues. Analyzing water risk and its spatial distribution is integral to the attainment of Sustainable Development Goal (SDG) 6, as this contributes to effective water resource partition management. In this paper, a compiling method of risk atlas with multiple layers is proposed, and the water risk system is divided into five sub-systems including the risk of resource, management, engineering, quality, and disaster. The information used for the risk atlas is calculated by a risk evaluation model based on a Pressure–State–Response (PSR) framework, hierarchical cluster, and set pair analysis (SPA). Risks in the Qinling Mountains of Shaanxi (as a case study) are evaluated and visualized. The results show that grades IV and V of engineering, disaster, and resource risk exceed 40%, indicating that they require prior control. The quality and management risks are not major, but there is still room for improvement. Overall, the risk atlas can effectively and objectively reflect the spatial distribution of water risk and provide a basis for the layout of water risk control measures

A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets

International audienceIn this paper, we propose a sextuple cross-coupled SRAM cell, namely SCCS18T, protected against double-node upsets. Since the proposed SCCS18T cell forms a large feedback loop for value retention and error interception, the cell can self-recover from all possible single-node upsets (SNUs) and a part of double-node upsets (DNUs). Moreover, the proposed cell has optimized operation speed due to the use of parallel access transistors. Simulation results demonstrate that the proposed SCCS18T cell can approximately save 65% read access time at the cost of 49% power dissipation and 50% silicon area on average, compared with the state-of-the-art hardened SRAM cells

Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS

International audienceWith the aggressive reduction of CMOS transistor feature sizes, the soft error rate of nano-scale integrated circuits increases exponentially. In this paper, we propose a novel costoptimized and robust latch, namely CRLHQ, hardened against quadruple-node-upsets (QNUs) for nanoscale CMOS technology. The latch mainly comprises a 5×5 matrix based on interlocked source-drain cross-coupled inverters to robustly store logic values. Owing to the redundant constructed feedback loops, the latch can recover from all possible QNUs. Simulation results demonstrate all key QNUs' recovery of the proposed CRLHQ latch. Simulation results also show that the latch can approximately reduce 44.3% D-Q delay, 7.3% silicon area and 14.2% delay-area-power product (DAPP), compared with the state-of-the-art same-type reference latch that can recover from any QNU

LDAVPM: A Latch Design with Algorithm-based Verification Protected against Multiple-Node-Upsets in Harsh Radiation Environments

International audienceIn deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to chargesharing-induced multiple-node-upsets (MNUs) in harsh radiation environments. Muller C-elements are widely used for latch hardening against MNUs, such as triple and even quadruple node-upsets. Existing latch verifications for error-recovery highly rely on EDA tools with complex error-injection combinations. In this paper, a latch design with algorithm-based verification protected against MNUs in harsh radiation environments, is proposed. Due to the formed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification results demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing same-type design

Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets

International audienceThe continuous advancement of CMOS technologies makes SRAMs more and more sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell designs, namely S4P8N and S8P4N, with enhanced self-recoverability from single-node upsets (SNUs) and Double-node upsets (DNUs). First, the S4P8N cell that has more redundant nodes and more access transistors is proposed. The cell has the following advantages: (1) it can self-recover from all possible SNUs; (2) it can self-recover from a part of DNUs; (3) it has small overhead in terms of power dissipation. Then, to reduce read and write access time, the S8P4N cell that uses a special feedback mechanism among its internal nodes is proposed. The cell has similar soft error tolerability as the S4P8N cell. Simulation results validate the high robustness of the proposed SRAM cells. These results also show that the write access time, read access time, and power dissipation of the S8P4N cell are reduced approximately by 29%, 20%, and 21% on average, at the cost of moderate silicon area, when compared with the state-of-the-art radiation-hardened SRAM cells